1) Field of the Invention
The invention relates to semiconductor integrated circuits and their manufacture. The invention relates to a process for programming Read only memories for semiconductor integrated circuits and more particularly, relates to a process for factory programming individual read only memory cells late in the processing sequence.
2) Description of the Prior Art
To make a ROM (Read only memory), it is necessary to fabricate a storage cell that maintains data after the applied power is turned off, that is, a storage cell having almost permanent data characteristics. The storage cells are generally mass data storage files where each cell corresponds to the presence or absence of a transistor. Data is programmed into the cells during their manufacture. The process of programming data is often called coding. Examples of cell coding methods include field oxide programming, implant programming, and through-hole programming.
Field oxide programming provides for two types of metal oxide semiconductor field effect transistors (MOSFET) by the use of different gate oxide layer thickness for each transistor type. Each oxide layer thickness corresponds to a different transistor threshold voltage. In programmed cells, the thickness of the gate oxide layer is about the same thickness as the field oxide, thereby providing a transistor which is permanently "off" or in a logic "0" state. Unprogrammed cells include typical thicknesses for the gate oxide layer so that the transistor is "on" or in a logic "1" state. A disadvantage of the field oxide programming method includes a longer product turn-around-time (TAT) as measured from the programming step. Much of the process occurs after programming the gate oxide layers of the cells.
Another programming technique is the threshold voltage implant method which changes the transistor threshold voltage by ion implanting the transistor gates for programmed cells. In n-channel devices, impurities such as boron are implanted into exposed gates which raise their threshold voltage. The implant forces the gates of the cells permanently to an "off" state. Unexposed gates are not implanted and therefore provide cells at an "on" state. Heavy implants, however, often create damage to the thin gate oxide region. Damage to the gate oxide region causes higher parasitic junction capacitance between the source (or drain) and channel region of the metal oxide semiconductor field effect (MOS) transistor. Higher parasitic junction capacitance leads to an increase in average word-line capacitance, and often results in slower speeds.
Another method of ROM programming includes selectively opening the contact holes for each transistor to drain. Such method called the through-hole contact programming technique was, in fact, the historical ROM programming method. The through-hole contact programming technique, however, requires a contact for every cell, thereby increasing the size of the cell array. Increasing the size of the cell array often provides a resulting device which has a lower cell density. Lower cell density typically corresponds to higher integrated circuit costs, and less memory capacity which is incompatible for the higher memory ROM devices.
It is often desirable to apply the ROM code onto the partially completed devices during a latter part of the manufacturing process. By applying the code at the latter process, it takes less time to process the wafer from that point to completion. Less time for completion corresponds to a faster product turn-around-time. As the life cycle of integrated circuits become shorter, it is typically desirable to fabricate products with shorter turn-around-times.
Industry relies on two general types of ROM array structures and combinations thereof using cells fabricated by the described methods. Such array structures include the serial ROM cell structure which is a NAND gate type structure and the parallel ROM cell structure known as the NOR gate type structure. Characteristics of NOR and NAND gate type structures are often competing.
A parallel NOR gate type structure includes a set of MOS transistors connected in parallel to the bit-line. The parallel structure typically increases the speed of the ROM but decreases bit or cell packing density. The lower density is caused by the use of a larger cell size. The larger cell size exists from the contacts needed for each cell.
Alternatively, a serial NAND gate type structure often increases cell packing density or bit density but provides a slower operation speed. The serial structure forms a denser structure since no contact holes are required. Higher memory requirements for state-of-art devices use the denser serial NAND gate type structure.
FIG. 1A is a cross-sectional view of a programmed cell 10 for a typical prior art ROM device fabricated by the threshold voltage implant method. The programmed cell may be used for a NAND gate type array structure. The threshold voltage implant method changes an enhancement mode n-channel metal oxide semiconductor field effect transistor (MOSFET) into a depletion mode device by implanting n-type ions into the channel region of the MOS transistor. The n-type implant programs or codes the transistor of the cell.
The programmed cell 11 includes a depletion mode MOS transistor in a semiconductor substrate 1. The programmed cell defines a p-type well region 20, field oxide regions 2, gate oxide region 4, and source/drain regions 12, 14. The programmed cell also defines an implanted channel region 15 under the gate oxide region 4. The implanted channel region changes the enhancement mode MOS transistor into the depletion mode transistor. A polysilicon gate 16, gate sidewall spacers 13, borophosphosilicate glass layer 30 (BPSG), metallization layer 70, and surface passivation 80 are also shown. The polysilicon gate, source region, drain region, and channel region define the depletion mode MOS-FET.
Each cell, such as the cell of FIG. 1A, corresponds to a region for storing bits of information in a ROM semiconductor integrated circuit chip. Thousands and even millions of these microscopically small regions make up a core memory area (or active cell area) of the ROM chip. The completed ROM chip also includes peripheral circuits, interconnects, and bonding pads.
A simplified ROM fabrication process of the inventor's may be briefly outlined as follows:
(1) Provide semiconductor substrate. PA0 (2) Grow gate oxide layer. PA0 (3) Deposit gate polysilicon layer and dope. PA0 (4) Mask 1: Define gate polysilicon layer to form polysilicon gate regions. PA0 (5) Mask 2: Define N- type LDD regions and implant. PA0 (6) Mask 3: Define P- type LDD regions and implant. PA0 (7) Form sidewall spacers on the polysilicon gate regions and densify. PA0 (8) Mask 4: Define N+ type source/drain regions and implant. PA0 (9) Mask 5: Define P+ type source/drain regions and implant. PA0 (9A) Wafers stored in wafer bank waiting for customer orders PA0 (10) Mask 6: Define exposed ROM code regions. PA0 (11) Implant exposed regions to provide ROM code. PA0 (12) Form oxide layer. PA0 (13) Deposit BPSG layer and reflow. PA0 (14) Mask 7: Define contact plug regions on BPSG layer. PA0 (15) Etch contact plug holes through BPSG and oxide layer. PA0 (16) Mask 8: Define contact plug implant regions and implant. PA0 (17) Anneal contact plug implant. PA0 (18) Sputter aluminum metallization. PA0 (19) Mask 9: Define aluminum metallization. PA0 (20) Deposit surface passivation layers. PA0 (21) Mask 10: Define pad regions with pad mask.
This sequence of processing steps codes or programs the ROM at steps 10 and 11. Prior to the programming steps, the partially completed wafer typically awaits for a customer ROM code at the wafer bank. After receiving the ROM code, the partially completed wafer is removed from the wafer bank, is coded, and undergoes the remaining process steps to form the completed wafer. The completed wafer then undergoes assembly and testing before the completed product is delivered to the customer.
Product TAT typically begins at mask 6 and ends upon shipping the packaged and tested product to the customer. The prior art fabrication method requires at least twelve major layers must be formed to complete the wafer and typically may take up to 28 days. The completed wafer then under goes assembly and testing which often takes additional days. It is often desirable to reduce the number of processing steps from the coding step to final testing of the device. Less steps after coding generally reduces product TAT for the customer.
A major challenge in ROM manufacturing is to reduce the turn around time by customizing the ROM by the code implant late in the process sequence. This should be done with an uncomplicated and low-cost process.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,514,609 (Chen et al.) shows a method of Code implant through Glass to reduce product delivery time. U.S. Pat. No. 5,561,624 (Chen et al.) teaches a method of ROM array coding after metallization. U.S. Pat. No. 4,513,494 (Batra) shows a method of late mask processing for RAM. The patent etches back through a silicon oxide layer down to a SiN stop layer. The code implant is performed through the SIN layer.
From the above it is seen that a method of fabricating semiconductor ROM devices that is easy, reliable, cost effective, and identifiable is often desired.